The bus architecture of a computer system substantially influences the manner in which information is communicated between the components of a computer system. In a typical computer system, one or more busses are used to connect a central processing unit (CPU) to a memory and to input/output elements. Typically the bus consists of several "lines" of electrically conductive material. The bus permits electrical signals representing data and control instructions to be readily transmitted between different components coupled to the bus. The order and speed at which the components interact with each other over the bus has a substantial impact on the performance of the computer system.
In order to maximize the benefit of computer systems, the electronics industry has engaged in activities to develop several types of progressively faster bus architectures. Recently, the PCI (peripheral component interconnect) bus architecture was developed to provide a high speed, low latency bus architecture from which a large variety of computer systems could be developed. The PCI bus architecture has become one of the most widely used and supported bus architectures in the industry.
Prior Art FIG. 1 shows a typical PCI bus architecture 100. PCI bus architecture 100 is comprised of a CPU 102 and a main memory 104, both coupled to a host PCI bridge arbiter 106 (hereafter PCI arbiter 106). CPU 102 is coupled to PCI arbiter 106 through a CPU local bus 108. Main memory 104 is coupled to PCI arbiter 106 by memory bus 110. The PCI bus 112 is coupled to arbiter 106 and to each of the PCI compliant devices or "agents" 114, 116, 118, 120, 122, and 124 respectively. Each of the PCI agents 114, 116, 118, 120, 122, and 124 (hereafter referred to collectively as PCI agents 114-124) residing on PCI bus 112 use PCI bus 112 to transmit and receive information and signals. PCI bus 112 is comprised of functional signal lines and data lines; for example, interface control lines, address/data lines, error signal lines, and the like. PCI agents 114-124 follow a definitive set of protocols and rules designed to standardize the method of accessing, utilizing, and relinquishing PCI bus 112. The PCI bus protocols and specifications are set forth in an industry standard PCI specification (e.g., PCI Specification--Revision 2.1).
In accordance with the industry standard PCI specification, only one data transaction can take place on a PCI bus at any given time. To ensure this requirement is enforced, the typical PCI bus system has a PCI arbiter that controls access to the PCI bus. When one of the PCI agents 114-124 requires the use of PCI bus 112 to transmit or receive data, the PCI agent requests PCI bus 112 "ownership" from PCI arbiter 106. The PCI agent requesting ownership is referred to as a PCI initiator agent, or master device. The term master device is generically used in bus systems, including systems other than PCI. The PCI agent the PCI initiator agent is attempting to communicate with is referred to as a PCI target agent (e.g., main memory 104) or slave device. The term slave device is generically used in bus systems, including bus systems other than PCI. Typically, each of the PCI agents 114-124 may independently act as a PCI initiator agent and request the PCI bus ownership. Thus, at any given time several of the PCI agents 114-124 may be requesting the PCI bus ownership simultaneously. Where there are simultaneous requests for PCI bus ownership, PCI arbiter 106 arbitrates between requesting PCI initiator agents to determine which requesting PCI initiator agent will be granted PCI bus ownership.
Each device needs ownership of the PCI bus in accordance with its respective requirements. These requirements include, for example, latency tolerance, data transfer bandwidth, block transfer size, and the like. Each device should have a differing priority status with regard to their respective requests for PCI bus ownership. Some devices are more critical to the proper operation of the computer system than others, some devices are less tolerant of latency than others, and some devices need to transfer very large quantities of data. If the arbiter grants PCI bus access in an erratic or arbitrary manner there is no assurance that the computer system will operate effectively. However, if devices with more critical requirements are assured a better chance of obtaining bus access, the computer system will operate more efficiently. Thus, the order in which master devices access a bus is very important and often critical to the optimal operation of the computer system. Typically, the order in which devices access a bus is set forth in an arbitration priority scheme
FIG. 2 shows a typical prior art fixed priority arbitration scheme 200. Fixed priority arbitration scheme 200 shows the relative priority of 7 coupled devices, device 0 through device 6, where device 0 is the highest priority device and device 6 is the lowest priority PCI agent. For example, a network adapter card typically has a requirement that it transfer very large blocks of data from the network to main memory, which requires a disproportionately large amount of PCI bus data transfer bandwidth. The network adapter also typically has internal buffers of limited size, which cannot tolerate data transfer latency without incurring a buffer overrun or underrun. Consequently, the network adapter would typically be coupled as device 0. In contrast, typically a printer does not have a requirement to transfer particularly large blocks of data, is typically very tolerant of latency, and thus would typically be coupled as device 6. Thus, devices with rigorous requirements are allocated higher priority in arbitration priority scheme 200 (e.g., device 0) while devices with relatively less rigorous requirements are allocated lower priority (e.g., device 6).
Despite the potential benefits of the above priority arbitration system, it has several flaws. When any other device requests bus ownership simultaneously with device 0, the other device is always denied bus access and device 0 always receives ownership first. Lower priority devices may not be granted sufficient access to the bus because they can be prevented from acquiring ownership for long periods of time. That is, lower priority devices may be "starved" of PCI bus bandwidth, especially in computer systems where there are many high bandwidth devices. Hence, arbitration priority scheme 200 does not ensure low priority devices will be granted adequate PCI bus access.
Resolving problems associated with arbitration systems is typically very difficult and entails the expenditure of significant engineering resources. For example, an apparent simple resolution to the "starvation" problem would be to give all the devices an equal opportunity to access the bus. However, as indicated above, devices typically have differing requirements. As a result, simply assigning each device the same priority typically means PCI bus access time is not being assigned in a manner that permits the computer system to operate optimally. If adequate attention is not given to the arbitration priority scheme the computer system may not work at all. Consistently sustaining the high transaction (e.g. data transfer) rates across a PCI bus typically demanded by a computer system requires efficient allocation of PCI bus ownership.
Efficiently managing the priority allocation of the PCI bus is essential to the proper operation of a computer system. As described above, only one device at a time can transfer data across the PCI bus, and the PCI arbiter determines which device is granted PCI bus access. When the PCI arbiter receives competing requests for bus ownership, the PCI arbiter assigns access to the PCI bus based on the relative priority of the devices. Typically, some devices are more important to the functionality of the computer system than other devices and are thus considered a higher priority. The arbiter needs to ensure that PCI bus access is allocated among the competing devices based upon the relative priority of the devices' requirements. To accomplish this, the arbiter typically follows a predetermined arbitration priority scheme (or arbitration methodology) based on the devices in the computer system and their respective requirements.
Given the arbitration priority scheme is typically based on the respective requirements of devices in the computer system, the most efficient arbitration priority scheme is not ascertainable until after the devices of a particular computer system are designed and their requirements ascertained. Previously, an optimal design for the PCI arbiter could not be designed until after the PCI initiator agents and PCI target agents of a particular computer system were designed. Thus, engineering resources committed to the arbiter design are essentially "on hold" until after the rest of the computer system is designed. In addition, waiting to design the arbiter means that there are significant delays in production of the final product and in realization of the advantages associated with new computer system designs.
Other current technology limitations adversely affect arbitration design and implementation. As indicated above, it is possible for the requirements of PCI initiator agents and PCI target agents to vary greatly. Since an arbiter's priority allocation is based upon the specific requirements of the devices in a particular computer system, it is unlikely the PCI arbiter for a particular computer system contains the most efficient arbitration priority scheme for a different computer system. Thus, existing arbiters effectively have to be thrown out when a new computer system is designed. That is, new arbiters have to be designed and manufacturing processes reengineered for each new computer system. The present state of arbiter technology is lacking some significant desirable attributes.
What is required is a single reconfigurable priority arbitration system with flexible reprogrammable arbitration priority schemes. The required priority arbitration system should efficiently allocate PCI bus bandwidth to optimize the overall functionality of the computer system. The priority arbitration system should be capable of adjusting to changes in device requirements and addressing complex priority allocation parameters. The required solution needs to ensure devices with stringent requirements that demand significant PCI bus bandwidth are assigned a relatively high priority and properly served, while providing low priority devices with sufficient bus access time to guarantee they are not "starved". The present invention provides a novel solution to the above requirements.